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low power audio codec preliminary technical data ssm2602 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features stereo, 24-bit analog-to-digital and digital-to-analog converters dac snr: 98 db (a-weighted), thd: ?80 db at 48 khz, 3.3 v adc snr: 90 db (a-weighted), thd: ?80 db at 48 khz, 3.3 v highly efficient headphone amplifier complete stereo/mono or microphone/line interface low power 7 mw stereo playback (1.8 v/1.8 v supplies) 14 mw record and playback (1.8 v/1.8 v supplies) low supply voltages analog: 1.8 v to 3.6 v digital core: 1.8 v to 3.6 v digital i/o: 1.8 v/3.6 v 256 f s /384 f s or usb master clock rate: 12 mhz, 24 mhz audio sample rates: 8 khz,16 khz, 32 khz, 44.1 khz, 48 khz, 88.2 khz, and 96 khz 28-lead, 5 mm 5 mm lfcsp (qfn) package applications mobile phones mp3 players portable gaming portable electronics educational toys general description the ssm2602 is a low power, high quality stereo audio codec for portable digital audio applications with stereo programmable gain amplifier (pga) line and monaural microphone inputs. it features two 24-bit analog-to-digital converter (adc) channels and two 24-bit digital-to-audio (dac) converter channels. the ssm2602 can operate as a master or a slave. it offers various master clock frequencies, including 12 mhz or 24 mhz for usb devices; standard 256 f s rates, such as 12.288 mhz and 24.576 mhz; and many common audio-sampling rates, such as 96 khz, 88.2 khz, 48 khz, 44.1 khz, 32 khz, 16 khz, and 8 khz. the ssm2602 can operate at power supplies as low as 1.8 v for the analog circuitry and 1.5 v for the digital circuitry. the maximum voltage supply is 3.6 v for all supplies. the ssm2602 software-programmable output options provide the user with many application options, such as speaker driver, headphone driver, or both. its volume control functions provide a large range of gain control of the audio signal. the ssm2602 is specified over the industrial temperature range of ?40c to +85c. it is available in a 28-lead, 5 mm 5 mm lead frame chip scale package (lfcsp). functional block diagram avdd v mid agnd dbvdd dgnd dcvdd hpvdd pgnd micbias rhpout rout micin digital processor rlinein mux adc llinein mux adc dac dac lout lhpout atten atten atten atten clk mclk/ xti xto clkout control interface mode csb sdin sclk digital audio interface dacdat adcdat bclk daclrc adclrc bypass/mute 3db step ?34.5db~+33db, 1.5db step 14db/34db ?34.5db~+33db, 1.5db step ?73db~+6db, 1db step ?73db~+6db, 1db step 6db~15db/mute 3db step 6db~15db/mute 3db step bypass/mute 3db step 06858-001 ssm2602 figure 1.
ssm2602 preliminary technical data rev. prb | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended operating conditions ...................................... 4 digital filter characteristics ....................................................... 4 timing characteristics ................................................................ 5 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 converter filter response ........................................................... 8 digital de-emphasis characteristics ......................................... 9 theory of operation ...................................................................... 10 adc high-pass filter ................................................................ 10 automatic level control (alc) ............................................... 10 analog interface ......................................................................... 11 digital audio interface .............................................................. 11 software control interface ........................................................ 13 applications ..................................................................................... 14 typical application circuits ......................................................... 15 register map ................................................................................... 17 register map details ...................................................................... 18 left-channel adc input volume, address 0x00 .................. 18 right-channel adc input volume, address 0x01 ............... 19 left-channel dac volume, address 0x02 ............................. 20 right-channel dac volume, address 0x03 .......................... 20 analog audio path, address 0x04 ........................................... 21 digital audio path control, address 0x05 ............................. 21 power management, address 0x06 .......................................... 22 power consumption .................................................................. 22 digital audio i/f, address 0x07 ............................................... 23 sampling rate, address 0x08 .................................................... 23 active, address 0x09 ............................................................. 25 reset, address 0x0f ................................................................. 25 alc control 1, address 0x10 ................................................... 25 alc control 2, address 0x11 ................................................... 26 noise gate, address 0x12 .......................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 9/07revision prb: preliminary version
preliminary technical data ssm2602 rev. prb | page 3 of 28 specifications t a = 25c, avdd = dvdd = 3.3 v, pvdd = 3.3 v, 1 khz signal, f s = 48 khz, pga gain = 0 db, 24-bit audio data, unless otherwise noted. table 1. parameter min typ max unit conditions operating conditions analog voltage supply (avdd) 1.8 3.3 3.6 v digital power supply 1.5 3.3 3.6 v ground (agnd, pgnd, dgnd) 0 v power consumption power-up stereo record (1.8 v) 7 mw stereo record (3.3 v) 22 mw stereo playback (1.8 v) 7 mw stereo playback (3.3 v) 22 mw power-down 40 w line input input signal level (0 db) 1 avdd/3.3 v rms 200 k pga gain = 0 db 10 k pga gain = +33 db input impedance 480 k pga gain = ?34.5 db input capacitance 10 pf 85 90 db pga gain = 0 db, avdd = 3.3 v signal-to-noise ratio (a-weighted) 87 db pga gain = 0 db, avdd = 1.8 v ?80 db ?1 dbfs input, avdd = 3.3 v total harmonic distortion (thd) ?75 db ?1 dbfs input, avdd = 1.8 v channel separation 80 db programmable gain ?34.5 0 33.5 db gain step 1.5 db mute attenuation ?80 db microphone input input signal level 1 v rms signal-to-noise ratio (a-weighted) 85 db microphone gain = 0 db (r source = 40 k) total harmonic distortion ?70 db 0 dbfs input, 0 db gain power supply rejection ratio 50 db mute attenuation 80 db input resistance 10 k input capacitance 10 pf microphone bias bias voltage 0.75 avdd v bias current source 3 ma noise in the signal bandwidth 40 nv/hz 20 hz to 20 khz line output dac ?1 dbfs input dac + line output full-scale output 1 avdd/3.3 v rms 100 db avdd = 3.3 v signal-to-noise ratio (a-weighted) 98 avdd = 1.8 v ?80 db avdd = 3.3 v thd + n ?75 avdd = 1.8 v power supply rejection ratio 50 db channel separation 80 db
ssm2602 preliminary technical data rev. prb | page 4 of 28 4 parameter min typ max unit conditions headphone output full-scale output voltage 1 avdd/3.3 v rms 30 mw r l = 32 maximum output power 60 mw r l = 16 signal-to-noise ratio (a-weighted) 92 100 db ?50 db p out = 10 mw thd + n ?55 db p out = 20 mw power supply rejection ratio 50 db mute attenuation 80 db line input to line output full-scale output voltage 1 avdd/3.3 v rms signal-to-noise ratio (a-weighted) 96 db total harmonic distortion ?80 db power supply rejection 50 db microphone input to headphone output full-scale output voltage 1 avdd/3.3 v rms signal-to-noise ratio (a-weighted) 98 db power supply rejection ratio 50 db programmable attenuation 6 15 db gain step 3 db mute attenuation 80 db recommended operat ing conditions table 2. parameter min typ max unit analog voltage supply (avdd) 1.8 3.3 3.6 v digital power supply 1.5 3.3 3.6 v ground (agnd, pgnd, dgnd 0 v digital filter characteristics table 3. parameter min typ max unit conditions adc filter pass band 0 0.445 f s hz 0.04 db 0.5 f s hz ?6 db pass-band ripple 0.04 db stop band 0.555 f s hz stop-band attenuation ?60 db f > 0.567 f s high-pass filter corner frequency 3.7 hz ?3 db 10.4 hz ?0.5 db 21.6 hz ?0.1 db dac filter pass band 0 0.445 f s hz 0.03 db 0.5 f s hz ?6 db pass-band ripple 0.04 db stop band 0.555 f s hz stop-band attenuation ?58 db f > 0.565 f s
preliminary technical data ssm2602 rev. prb | page 5 of 28 timing characteristics table 4. limit parameter t min t max unit description f sclk 0 550 khz sclk frequency t sclkpl 1.3 s sclk low pulse width t sclkph 600 ns sclk high pulse width t sch 600 ns hold time (start condition) t scs 600 ns setup time (start condition) t ds 100 ns data setup time t sdin-sclkr 300 ns sdin, sclk rise time t sdin-sclkf 300 ns sdin, sclk fall time t hcs 600 ns setup time (hold condition) t dh 900 ns data hold time timing diagrams tbd
ssm2602 preliminary technical data rev. prb | page 6 of 28 6 absolute maximum ratings at 25c, unless otherwise noted. table 5. parameter rating supply voltage 5 v input voltage v dd common-mode input voltage v dd storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja jc unit 28-lead, 5 mm 5 mm lfcsp tbd tbd c/w esd caution
preliminary technical data ssm2602 rev. prb | page 7 of 28 pin configuration and fu nction descriptions pin 1 indicator 1 mclk/xti 2 xto 3 dcvdd 4 dgnd 5 dbvdd 6 int/clkout 7 bclk 17 rout 18 avdd 19 agnd 20 vmid 21 micbias 16 lout 15 pgnd 8 d a c d a t 9 d a c l r c 1 0 a d c d a t 1 2 h p v d d 1 3 l h p o u t 1 4 r h p o u t 1 1 a d c l r c 2 4 l l i n e i n 2 5 m o d e 2 6 c s b 2 7 s d i n 2 8 s c l k 2 3 r l i n e i n 2 2 m i c i n top view (not to scale) ssm2602 06858-002 figure 2. pin configuration of ssm2602 table 7. pin function descriptions pin no. mnemonic type description 1 mclk/xti digital input master clock input/crystal input 2 xto digital output crystal output 3 dcvdd digital supply digital core supply 4 dgnd digital ground digital ground 5 dbvdd digital supply digital i/o supply 6 clkout digital output buffered clock output 7 bclk digital input/output digital audio bit clock. this pi n is pulled down when the active register is set to 0. 8 dacdat digital input dac digital audio data input 9 daclrc digital input/output dac sample rate clock (from left and right channels). this pin is pulled down when the active register is set to 0. 10 adcdat digital output adc digital audio data output 11 adclrc digital input/output adc sample rate clock (from left and right channels). this pin is pulled down when the active register is set to 0. 12 hpvdd analog supply headphone supply 13 lhpout analog output left-channel headphone output 14 rhpout analog output right-channel headphone output 15 pgnd analog ground headphone ground 16 lout analog output left-channel line output 17 rout analog output right-channel line output 18 avdd analog supply analog supply 19 agnd analog ground analog ground 20 vmid analog output middle voltage decoupling capacitor 21 micbias analog output microphone bias 22 micin analog input microphone input signal 23 rlinein analog input right- channel line/microphone input 24 llinein analog input left-channel line/microphone input 25 mode digital input control interface selection to select i 2 c?/spi 26 csb digital input 3-wire mpu chip select/2-wire mpu interface address selection, active low. this pin is pulled up when the active register is set to 0. 27 sdin digital input/output 3-wire mpu da ta input/2-wire mpu data input/output 28 sclk digital input 3-wire mpu clock input/2-wire mpu clock input
ssm2602 preliminary technical data rev. prb | page 8 of 28 8 typical performance characteristics converter filter response 06858-003 frequency ( f s ) magnitude (db) 00.5 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1.5 1.0 2.0 2.5 3.0 figure 3. adc digital filter frequency response 06858-005 frequency ( f s ) magnitude (db) 0 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.50 figure 4. adc digital filter ripple 06858-004 frequency ( f s ) magnitude (db) 00.5 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1.5 1.0 2.0 2.5 3.0 figure 5. dac digital filter frequency response 06858-006 frequency ( f s ) magnitude (db) 0 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.50 figure 6. dac digital filter ripple
preliminary technical data ssm2602 rev. prb | page 9 of 28 digital de-emphasis characteristics 0 6858-007 frequency ( khz ) magnitude (db) ?10 ?8 ?9 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 21 6 0 4 6 8 10 12 14 ?0.20 ?0.10 ?0.15 ?0.05 0 0.05 0.10 0.20 0.15 0 20 18 2 12 14 16 10 468 06858-011 frequency ( khz ) magnitude (db) figure 7. de-emphasis frequency response (32 khz) frequency ( khz ) magnitude (db) 1412 246810 06858-010 ?0.20 ?0.10 ?0.15 ?0.05 0 0.05 0.10 0.20 0.15 0 figure 8. de-emphasis error (32 khz) 24 22 2 4 6 8 10 12 14 16 18 20 06858-009 frequency ( khz ) magnitude (db) ?10 ?8 ?9 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0 figure 9. de-emphasis frequency response (44.1 khz) figure 10. de-emphasis error (44.1 khz) 22 06858-008 frequency ( khz ) magnitude (db) ?10 ?8 ?9 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 2468101214161820 0 figure 11. de-emphasis frequency response (48 khz) 20 18 2 12 14 16 10 468 06858-012 ?0.20 ?0.10 ?0.15 ?0.05 0 0.05 0.10 0.20 0.15 0 frequency ( khz ) magnitude (db) figure 12. de-emphasis error (48 khz)
ssm2602 preliminary technical data rev. prb | page 10 of 28 theory of operation adc high-pass filter dc offset can be removed by using the ssm2602 adjustable digital high-pass filter (see tabl e 3 for characteristics). digital filter characteristics the adc and dac employ separate digital filters. automatic level control (alc) codec has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. decay (gain ramp-up) time this is the time for the pga gain to ramp up through 90% of its range. the time for the recording level to return to its target value therefore depends on both the decay time and the gain adjustment required. if the gain adjustment is small, the time to return to the target value will be less than the decay time. attack (gain ramp-down) time this is the time for the pga gain to ramp down through 90% of its range. the time for the recording level to return to its target value therefore depends on both the attack time and the gain adjustment required. if the gain adjustment is small, the time to return to the target value will be less than the attack time. 0 6858-021 input signal pga signal after alc decay time alc target value attack time figure 13. pga and alc decay time and attack time definitions
preliminary technical data ssm2602 rev. prb | page 11 of 28 analog interface microphone input high impedance input mic tbd headphone output tbd sidetone insertion tbd digital audio interface the digital audio input can support various communication protocols: ? right justified ? left justified ? i 2 s mode ? digital-signal processor (dsp) mode the mode selection is performed by writing to the format [1:0] bits of the digital audio interface register (register r7). all modes are msb first and operate with data of 16 to 32 bits. 06858-013 adclrc/ daclrc bclk adcdat/ dacdat 1234 nn 1 2 left channel 3 right channel 1/ f s figure 14. left-justified audio interface 06858-014 adclrc/ daclrc bclk adcdat/ dacdat n 4321 1 n left channel 23 right channel 4 1/ f s figure 15. right-justified audio interface 06858-015 adclrc/ daclrc bclk adcdat/ dacdat 1234 n n 1 2 left channel 3 right channel 1/ f s figure 16. i 2 s audio interface
ssm2602 preliminary technical data rev. prb | page 12 of 28 06858-016 adclrc/ daclrc bclk adcdat/ dacdat 123 n n 1 2 left channel 3 right channel 1/ f s figure 17. dsp/pulse code modulation (pcm) mode audio interface submode 1 (sm1) [bit lrp = 0] 06858-017 adclrc/ daclrc bclk adcdat/ dacdat 123 n1 2 n left channel 3 right channel 1/ f s falling edge can occur any where in this area figure 18. dsp/pcm mode audio interface submode 2 (sm2) [bit lrp = 1]
preliminary technical data ssm2602 rev. prb | page 13 of 28 software control interface the software control interface can be operated with a 3-wire (spi) or 2-wire (i 2 c) interface. selection of the interface format is achieved by setting the state of the mode pin. table 8. selecting the interface format mode pin setting interface 0 2-wire (i 2 c) interface 1 3-wire (spi) interface in 3-wire (spi) mode, sdin is used for the program data, sclk is used to clock in the program data, and csb is used to latch in the program data. in 2-wire (i 2 c) mode, sdin is used for serial data, sclk is used for the serial clock, and the state of the csb pin allows the user to select one of two addresses (see table 9 ). table 9. selecting the address csb pin setting address 0 0011010 1 0011011 06858-018 b15 b14 csb cclk sdin b0 b01b02b03b04b05 b06b07 b08b09b10b11b12b13 notes 1. b15 to b9 are register map address. 2. b8 to b0 are register data. figure 19. spi serial interface 06858-019 p 98 1 ? 7 98 1 ? 7 98 1 ? 7 s sdata scloc k start addr r/w ack ack subaddress ack stop data figure 20. ssm2602 2-wire i 2 c generalized clocking diagram 0 6858-022 write sequence read sequence sa 1 a7 a0 a(s) a(s) s b15 b9 0 01 0p 0 ... a1 a7 a0 a(s) ... b0 b8 b7 a(m) a(m) ... b0 b7 p ... ... ... device address device address register address sa 1 a7 a0 a(s) a(s) a(s) b15 b9 b8 0 ... ... device address register address register data (slave drive) register data s/p = start/stop bit. a0 = i 2 c r/w bit. a(s) = acknowlege by slave. a (m) = acknowlege by master. a (m) = acknowlege by master. figure 21. ssm2602 i 2 c write and read sequences
ssm2602 preliminary technical data rev. prb | page 14 of 28 applications tbd
preliminary technical data ssm2602 rev. prb | page 15 of 28 typical application circuits 06858-020 avdd v mid avss dbvdd dvss dcvdd hpvdd hpvss micbias rhpout rout micin digital processor rlinein mux adc llinein mux adc dac dac lout lhpout atten osc clk gen os c c lk g e n mclk/ xti xto clkout control interface mode csb sdins clk digital audio interface dacdat adcdat bclk daclrc adclrc outpd dacpd adcpd ladcpd radcpd ldacpd rdacpd lhppd rhppd pwrpd ref micpd micbpd rinpd linpd linepd oscpd clkoutpd atten atten atten ssm2602 figure 22. ssm2602 power management functional location diagram
ssm2602 preliminary technical data rev. prb | page 16 of 28 06858-023 connection under chip csb sdin sclk daclrc dacdat adcdat adclrc bclk +3.3v_vaa +3.3v_vaa +3,3v_vdd j4 bnc 1 2 + c12 1uf r4 nc + c21 10uf r12 100 c26 220pf + c13 1uf + c3 10uf c5 220pf c27 220pf + c14 220uf r6 nc l1 fb c20 0.1uf c7 22pf c11 220pf + c15 220uf r8 0 c1 1uf r13 47k u1 ssm2602kcpz 18 12 5 3 24 23 21 22 9 8 10 11 7 25 26 27 28 1 2 19 15 4 17 16 13 14 6 20 avdd hpvdd dbvdd dcvdd l_line_in r_line_in mic_bias mic_in daclrc dacdat adcdat adclrc bclk mode csb sdin sclk mclk/xti por/xto avss hpvss dvss rout lout lhp_out rhp_out int/clkout vmid r15 47k c24 0.1uf j5 bnc 1 2 c2 1uf l2 fb r9 47k c10 1uf r1 0 j2 r 1 2 + c18 10uf c4 220pf c6 0.1uf j7 mic_in 1 2 r7 680 c23 0.1uf + c22 10uf r11 100 r2 nc r10 47k c8 22pf r5 100k c19 0.1uf r14 47k j6 phonejack stereo sw 1 2 3 4 5 y1 12.288mhz r3 0 + c25 10uf j1 l 1 2 spi[0..2] i2s[0..4] figure 23. ssm2602 typical application circuit
preliminary technical data ssm2602 rev. prb | page 17 of 28 register map table 10. register map reg. address name d8 d7 d6 d5 d4 d3 d2 d1 d0 default r0 0x00 left-channel adc input volume lrinboth linmute 0 linvol [5:0] 010010111 r1 0x01 right-channel adc input volume rlinboth rinmute 0 rinvol [5:0] 010010111 r2 0x02 left-channel dac volume lrhpboth lzcen lhpvol [6:0] 001111001 r3 0x03 right-channel dac volume rlhpboth rzcen rhpvol [6:0] 001111001 r4 0x04 analog audio path micboost2 sidetone_att [1:0] sidetone_en dacsel bypass insel mutemic micboost 000001010 r5 0x05 digital audio path 0 0 0 0 hpor dacmu deemph [1:0] adchpd 000001000 r6 0x06 power management 0 pwroff clkoutpd oscpd outpd dacpd adcpd micpd lineinpd 010011111 r7 0x07 digital audio i/f 0 bclkinv ms lrswap lrp wl [1:0] format [1:0] 000001010 r8 0x08 sampling rate 0 clkodiv2 clkdiv2 sr [3:0] bosr usb 000000000 r9 0x09 active 0 0 0 0 0 0 0 0 active 000000000 r15 0x0f software reset reset [8:0] 000000000 r16 0x10 alc control 1 alcsel [1:0] maxgain [2:0] alcl [3:0] 001111011 r17 0x11 alc control 2 0 dcy [3:0] atk [3:0] 000110010 r18 0x12 noise gate 0 ngth [4:0] ngg [1:0] ngat 000000000
ssm2602 preliminary technical data rev. prb | page 18 of 28 register map details left-channel adc input volume, address 0x00 table 11. left-channel adc input volume register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 lrinboth linmute 0 linvol [5:0] table 12. descriptions of left-channel adc input volume register bits bit name description settings lrinboth left-channel line input volume update 0 = store linvol in intermediate latch (default) 1 = update left- and right-channel gains linmute left-channel input mute 0 = disable mute 1 = enable mute (default) linvol [5:0] left-channel pga volume control 00 0000 = 34.5 db 1.5 db step down 01 0111 = 0 db (default) 1.5 db step down 01 1111 = 12 db 10 0000 = 13.5 db 10 0001 = 15 db 10 0010 = 16.5 db 10 0011 = 18 db 10 0100 = 19.5 db 10 0101 = 21 db 10 0110 = 22.5 db 10 0111 = 24 db 10 1000 = 25.5 db 10 1001 = 27 db 10 1010 = 28.5 db 10 1011 = 30 db 10 1100 = 31.5 db 10 1101 = 33 db 11 1111 to 10 1101 = 33 db
preliminary technical data ssm2602 rev. prb | page 19 of 28 right-channel adc input volume, address 0x01 table 13. right-channel input volume register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 rlinboth rinmute 0 rinvol [5:0] table 14. descriptions of right input volume register bits bit name description settings rlinboth right-channel line input volume update 0 = store rinvol in intermediate latch (default) 1 = update left- and right-channel gains rinmute right-channel input mute 0 = disable mute 1 = enable mute (default) rinvol [5:0] right-channel pga volume control 00 0000 = 34.5 db 1.5 db step down 01 0111 = 0 db (default) 1.5 db step down 01 1111 = 12 db 10 0000 = 13.5 db 10 0001 = 15 db 10 0010 = 16.5 db 10 0011 = 18 db 10 0100 = 19.5 db 10 0101 = 21 db 10 0110 = 22.5 db 10 0111 = 24 db 10 1000 = 25.5 db 10 1001 = 27 db 10 1010 = 28.5 db 10 1011 = 30 db 10 1100 = 31.5 db 10 1101 = 33 db 11 1111 to 10 1101 = 33 db
ssm2602 preliminary technical data rev. prb | page 20 of 28 left-channel dac volume, address 0x02 table 15. left-channel dac volume register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 lrhpboth lzcen lhpvol [6:0] table 16. descriptions of left-channel dac volume register bits bit name description settings lrhpboth right-channel headphone volume update 0 = store lhpvol in intermediate latch (default) 1 = update left- and right-channel gains lzcen left-channel zero cross detect enable 0 = disable (default) 1 = enable lhpvol [6:0] left-channel headphone volume control 000 0000 to 010 1111 = mute 011 0000 = ?73 db 111 1001 = 0 db (default) 1 db steps down to 111 1111 = +6 db right-channel dac volume, address 0x03 table 17. right-channel dac volume register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 rlhpboth rzcen rhpvol [6:0] table 18. descriptions of right-channel dac volume register bits bit name description settings rlhpboth right-channel headphone volume update 0 = store rhpvol in intermediate latch (default) 1 = update left- and right-channel gains rzcen right-channel zero cross detect enable 0 = disable (default) 1 = enable rhpvol [6:0] right-channel headphone volume control 000 0000 to 010 1111 = mute 011 0000 = ?73 db 111 1001 = 0 db (default) 1 db steps down to 111 1111 = +6 db
preliminary technical data ssm2602 rev. prb | page 21 of 28 analog audio path, address 0x04 table 19. analog audio path register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 micboost2 sidetone_att [1:0] sidetone_en dacsel bypass insel mutemic micboost table 20. descriptions of analog audio path register bits bit name description settings micboost2 additional microphone amplifier gain booster control 0 = 0 db (default) 1 = 20 db sidetone_att [1:0] microphone sidetone gain control 00 = ?6 db (default) 01 = ?9 db 10 = ?12 db 11 = ?15 db sidetone_en 0 = sidetone disable (default) 1 = sidetone enable dacsel dac select 0 = do not select dac (default) 1 = select dac bypass line input bypass to line output 0 = bypass disable 1 = bypass enable (default) insel microphone/line level boost 0 = microphone input select to adc (default) 1 = line input select to adc mutemic microphone mute control 0 = mute disable 1 = mute enable (default) micboost primary microphone amplifier ga in booster control 0 = 0 db (default) 1 = 20 db digital audio path control, address 0x05 table 21. digital audio path control register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 hpor dacmu deemph [1:0] adchpd table 22. descriptions of digital audio path control register bits bit name description settings hpor store dc offset when high-pass filter is disabled 0 = store offset disable (default) 1 = store offset enable dacmu dac digital mute 0 = no mute (signal active) 1 = mute (default) deemph [1:0] de-emphasis control 00 = no de-emphasis (default) 01 = 32 khz sampling rate 10 = 44.1 khz sampling rate 11 = 48 khz sampling rate adchpd adc high-pass filter control 0 = adc high-pass filter disable (default) 1 = adc high-pass filter enable
ssm2602 preliminary technical data rev. prb | page 22 of 28 power management, address 0x06 table 23. power management register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 pwroff clkoutpd oscpd outpd dacpd adcpd micpd lineinpd table 24. bit name description settings pwroff whole chip power-down control 0 = power up 1 = power down (default) clkoutpd clock output power-down control 0 = power up (default) 1 = power down oscpd crystal power-down control 0 = power up (default) 1 = power down outpd output power-down control 0 = power up 1 = power down (default) dacpd dac power-down control 0 = power up 1 = power down (default) adcpd adc power-down control 0 = power up 1 = power down (default) micpd microphone input power-down control 0 = power up 1 = power down (default) lineinpd line input power-down control 0 = power up 1 = power down (default) power consumption table 25. mode pwroff clkoutpd oscpd outpd dacpd adcpd micpd lineinpd avdd (3.3 v) hpvdd (3.3 v) dcvdd (1.5 v) dbvdd (1.5 v) unit record and playback 0 0 0 0 0 0 0 0 8.36 1.7 tbd tbd ma playback only oscillator enabled 0 0 0 0 0 1 1 1 3.1 1.7 tbd tbd ma external clock 0 1 1 0 0 1 1 1 3.1 1.7 tbd tbd ma record only line clock 0 0 0 1 1 0 1 0 3.15 - tbd tbd ma line oscillator 0 0 1 1 1 0 1 0 3.15 - tbd tbd ma microphone 1 0 0 0 1 1 0 0 1 3.45 - tbd tbd ma microphone 2 0 0 1 1 1 0 0 1 3.45 tbd tbd ma sidetone (microphone to headphone output) external clock 0 0 1 0 1 1 0 1 2.24 1.7 tbd tbd ma internally generated clock 0 0 1 0 1 1 0 1 2.24 1.7 tbd tbd ma analog bypass (line input or line output) external line 0 0 1 0 1 1 1 0 1.94 1.7 tbd tbd ma internally generated line 0 0 1 0 1 1 1 0 1.94 1.7 tbd tbd ma power-down external clock 1 1 1 1 1 1 1 1 tbd tbd tbd tbd ma oscillator 1 1 1 1 1 1 1 1 tbd tbd tbd tbd ma
preliminary technical data ssm2602 rev. prb | page 23 of 28 digital audio i/f, address 0x07 table 26. digital audio i/f register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 bclkinv ms lrswap lrp wl [1:0] format [1:0] table 27. descriptions of digital audio i/f register bits bit name description settings bclkinv bclk inversion control 0 = bclk not inverted (default) 1 = bclk inverted ms master mode enable 0 = enable slave mode (default) 1 = enable master mode lrswap swap dac data control 0 = output left- and right- channel data as normal (default) 1 = swap left- and right-channel dac data in audio interface lrp polarity control for clocks in right justified, left justified, and i 2 s modes 0 = normal daclrc and adclrc (default), or dsp submode 1 1 = invert daclrc and adclrc polarity, or dsp submode 2 wl [1:0] data-word length control 00 = 16 bits 01 = 20 bits 10 = 24 bits (default) 11 = 32 bits format [1:0] digital audio input format control 00 = right justified 01 = left justified 10 = i 2 s format (default) 11 = dsp mode sampling rate, address 0x08 table 28. sampling rate register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 clkodiv2 clkdiv2 sr [3:0] bosr usb table 29. descriptions of sampling rate register bits bit name description settings clkodiv2 clkout divider select 0 = clkout is core clock (default) 1 = clkout is core clock divided by 2 clkdiv2 core clock divide select 0 = core clock is mclk (default) 1= core clock is mclk divided by 2 sr [3:0] clock setting condition see table 30 and table 31 . bosr base oversampling rate usb mode: 0 = 250 f s (default) 1 = 272 f s normal mode: 0 = 256 f s (default) 1 = 384 f s usb usb mode select 0 = usb mode disable (default) 1 = usb mode enable
ssm2602 preliminary technical data rev. prb | page 24 of 28 table 30. sampling rate lookup table, usb disabled sampling rate register setting bosr sr3 sr2 sr1 sr0 normal/usb mclk (mhz) adc sampling rate (khz) dac sampling rate (khz) 0 0 12.288 1 0 0 0 0 0 18.432 48 48 0 0 12.288 1 0 0 0 1 0 18.432 48 8 0 0 12.288 1 0 0 1 0 0 18.432 8 48 0 0 12.288 1 0 0 1 1 0 18.432 8 8 0 0 12.288 1 0 1 0 0 0 18.432 12 12 0 0 12.288 1 0 1 0 1 0 18.432 16 16 0 0 12.288 1 0 1 1 0 0 18.432 32 32 0 0 12.288 1 0 1 1 1 0 18.432 96 96 0 0 11.2896 1 1 0 0 0 0 16.9344 44.1 44.1 0 0 11.2896 1 1 0 0 1 0 16.9344 44.1 8.02 0 0 11.2896 1 1 0 1 0 0 16.9344 8.02 44.1 0 0 11.2896 1 1 0 1 1 0 16.9344 8.02 8.02 0 0 11.2896 1 1 1 0 0 0 16.9344 11 11 0 0 11.2896 1 1 1 0 1 0 16.9344 22 22 0 0 11.2896 1 1 1 1 0 0 16.9344 24 24 0 0 11.2896 1 1 1 1 1 0 16.9344 88.2 88.2 table 31. sampling rate lookup table, usb enabled sampling rate register setting bosr sr3 sr2 sr1 sr0 normal/usb mclk (mhz) adc sampling rate (khz) dac sampling rate (khz) 0 0 0 0 0 1 12 48 48 1 1 0 0 0 1 12 44.1 44.1 0 0 0 0 1 1 12 48 8 1 1 0 0 1 1 12 44.1 8.02 0 0 0 1 0 1 12 8 48 1 1 0 1 0 1 12 8.02 44.1 0 0 0 1 1 1 12 8 8 1 1 0 1 1 1 12 8.02 8.02 0 0 1 0 0 1 12 12 12 0 0 1 0 1 1 12 16 16 0 1 1 0 0 1 12 11 11 0 1 1 0 1 1 12 22 22 0 1 1 1 0 1 12 24 24
preliminary technical data ssm2602 rev. prb | page 25 of 28 sampling rate register setting bosr sr3 sr2 sr1 sr0 normal/usb mclk (mhz) adc sampling rate (khz) dac sampling rate (khz) 0 0 1 1 0 1 12 32 32 0 0 1 1 1 1 12 96 96 1 1 1 1 1 1 12 88.2 88.2 active, address 0x09 table 32. active register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 active table 33. descriptions of active register bit bit name description settings active digital core activation control 0 = disable digital core (default) 1 = activate digital core reset, address 0x0f table 34. reset register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 reset [8:0] table 35. descriptions of reset register bits bit name description settings reset [8:0] write to reset register to set all control registers to default setting. 0 = reset (default) alc control 1, address 0x10 table 36. alc control 1 register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 alcsel [1:0] maxgain [2:0] alcl [[3:0] table 37. descriptions of alc control 1 register bits bit name description settings alcsel [1:0] alc selection 00: alc disabled (default) 01: alc enabled, right channel only 10: alc enabled, left channel only 11: n/a maxgain [2:0] pga maximum gain 000: ?12 db 001: ?6 db 6 db steps up to 111: 30 db (default) alcl [3:0] alc target level 0000: ?28.5 dbfs 0001: ?27 dbfs 1011: ?12 dbfs (default) 1.5 db steps up to 1111: ?6 dbfs
ssm2602 preliminary technical data rev. prb | page 26 of 28 alc control 2, address 0x11 table 38. alc control 2 register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 dcy [3:0] atk [3:0] table 39. descriptions of alc control 2 register bits bit name description settings dcy [3:0] decay (release) time control 0000: 24 ms 0001: 48 ms 0010: 96 ms 0011: 192 ms (default) 24 ms steps up to 1010: 24.576 sec atk [3:0] alc attack time control 0000: 6 ms 0001: 12 ms 0010: 24 ms (default) 6 ms steps up to 1010: 6.144 sec noise gate, address 0x12 table 40. noise gate register bit map d8 d7 d6 d5 d4 d3 d2 d1 d0 0 ngth [4:0] ngg [1:0] ngat table 41. descriptions of noise gate register bits bit name description settings ngth [4:0] noise gate thresh old 00000: ?76.5 dbfs (default) 00001: ?75 dbfs 1.5 db steps up to 11110: ?31.5 dbfs 11111: ?30 dbfs ngg [1:0] noise gate type x0: ho ld pga gain constant (default) 1 01: mute output 11: reserved ngat noise enable 0: noise disable (default) 1: noise enable 1 x = dont care.
preliminary technical data ssm2602 rev. prb | page 27 of 28 outline dimensions compliant to jedec standards mo-220-vhhd-1 pin 1 indi c ator top view 5.00 bsc sq 0.75 0.60 0.50 3.00 ref 0.50 bsc 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 4.75 bsc sq 1 28 7 8 22 21 14 15 0.25 min exposed pad (bottom view) 122106-a 0.30 0.23 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 seating plane coplanarity 0.08 0.05 max 0.02 nom figure 24. 28-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-28-4) dimensions shown in millimeters ordering guide model temperature range package description package option ssm2602cpz-r2 1 ?40c to +85c 28-lead lead frame chip scale package [lfcsp_vq] cp-28-4 ssm2602cpz-reel 1 ?40c to +85c 28-lead lead frame chip scale package [lfcsp_vq] cp-28-4 ssm2602cpz-reel7 1 ?40c to +85c 28-lead lead frame chip scale package [lfcsp_vq] cp-28-4 ssm2602-evalz 1 evaluation board 1 z = rohs compliant part.
ssm2602 preliminary technical data rev. prb | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr06858-0-9/07(prb)

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